1. Technical Field
The present invention relates to a clock generating circuit for an exchange system, and more particularly, relates to such a clock generating circuit and method for an exchange system capable of maintaining the constant timing in a range from a most significant clock to a least significant clock and redundancy synchronization.
2. Background Art
Generally, an exchange system improve reliability by using redundancy modules in a parallel fashion to insure that a particular task is carried through completion even when one of the modules becomes impaired. Such a redundant system is tolerant of faults as disclosed, for example, in U.S. Pat. No. 5,117,442 for Methods And Circuits For Synchronizing Signals In A Modular Redunaant Fault Tolerant Computer System issued to Hall, U.S. Pat. No. 5,377,205 for Fault Tolerant Clock With Synchronized Reset issued to Shi, U.S. Pat. No. 5,377,206 for Multiple-Channel Fault-Tolerant Clock System issued to Smith, and U.S. Pat. No. 5,537,655 for Synchronized Fault Tolerant Reset issued to Truong.
In such an exchange system employing redundancy modules, it is desirable that redundancy modules perform operations in synchronization with respect to other parallel modules. Conventional redundancy synchronization system which seeks to establish such synchronization typically requires synchronization of respective system clocks of high and low frequency bands between redundancy modules. While there are other clock synchronization systems known in the art as disclosed, for example, in U.S. Pat. No. 5,459,764 for Clock Synchronization System issued to Ohgami et al., it is my observation that none is available to synchronize clocks generated from redundancy modules with a constant timing in the range from a most significant clock to a least significant clock.